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INTEGRATED CIRCUITS
83C453/87C453 80C51 8-bit microcontroller family 8K/256 OTP/ROM, expanded I/O
Preliminary specification Supersedes data of 1997 Dec 29 IC20 Data Handbook 1998 Apr 23
Philips Semiconductors
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family 8K/256 OTP/ROM, expanded I/O
83C453/87C453
DESCRIPTION
The Philips 8XC453 is an I/O expanded single-chip microcontroller fabricated with Philips high-density CMOS technology. Philips epitaxial substrate minimizes latch-up sensitivity. The 8XC453 is a functional extension of the 87C51 microcontroller with three additional I/O ports and four I/O control lines. The 8XC453 is available in 68-pin LCC packages. Four control lines associated with port 6 facilitate high-speed asynchronous I/O functions. The 87C453 includes an 8k x 8 EPROM, a 256 x 8 RAM, 56 I/O lines, two 16-bit timer/counters, a seven source, two priority level, nested interrupt structure, a serial I/O port for either a full duplex UART, I/O expansion, or multi-processor communications, and on-chip oscillator and clock circuits. The 87C453 has two software selectable modes of reduced activity for further power reduction; idle mode and power-down mode. Idle mode freezes the CPU while allowing the RAM, timers, serial port, and interrupt system to continue functioning. Power-down mode freezes the oscillator, causing all other chip functions to be inoperative while maintaining the RAM contents.
FEATURES
* 80C51 based architecture * Seven 8-bit I/O ports * Port 6 features:
- Eight data pins - Four control pins - Direct MPU bus interface - ISA Bus Interface - Parallel printer interface - IBF and OBF interrupts - A flag latch on host write
* On the microcontroller:
- 8k x 8 EPROM Quick pulse programming algorithm Two-level program security system - 256 x 8 RAM - Two 16-bit counter/timers - Two external interrupts
* External memory addressing capability
- 64k ROM and 64k RAM
* Low power consumption:
- Normal operation: less than 24mA at 5V, 16MHz - Idle mode - Power-down mode
* Reduced EMI * Full-duplex enhanced UART
- Framing error detection - Automatic address recognition
ORDERING INFORMATION
EPROM1 P87C453EBAA OTP ROM P83C453EBAA TEMPERATURE C AND PACKAGE 68-Pin Plastic Leaded Chip Carrier, 0 to +70 FREQ. (MHz) 3.5 to 16 PKG. DWG # SOT188-3
NOTE: 1. OTP = One-Time Programmable EPROM.
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Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family 8K/256 OTP/ROM, expanded I/O
83C453/87C453
BLOCK DIAGRAM
P0.0-P0.7 P2.0-P2.7 P4.0-P4.7 P5.0-5.7
PORT 0 DRIVERS VCC VSS RAM ADDR REGISTER 256 BYTES RAM PORT 0 LATCH
PORT 2 DRIVERS
PORT 4 DRIVERS
PORT 5 DRIVERS
PORT 2 LATCH
PORT 4 LATCH
PORT 5 LATCH
8K x 8 EPROM
B REGISTER
ACC
STACK POINTER
TMP2
TMP1
PROGRAM ADDRESS REGISTER
BUFFER ALU PCON PSW TL1 PSW CSR SCON TMOD TH0 DPH SBUF TL0 DPL IE TCON TH1 AUXR IP PC INCREMENTER
INTERRUPT, SERIAL PORT AND TIMER BLOCKS
PROGRAM COUNTER PSEN ALE/PROG EAVPP RST PD TIMING AND CONTROL INSTRUCTION REGISTER
DPTR
PORT 1 LATCH
PORT 6 LATCH
PORT 3 LATCH
OSCILLATOR PORT 1 DRIVERS XTAL1 XTAL2 PORT 6 DRIVERS PORT 6 CONTROL/STATUS PORT 3 DRIVERS
P1.0-P1.7
P6.0-P6.7
IDS ODS BFLAG AFLAG
P3.0-P3.7
SU00158
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Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family 8K/256 OTP/ROM, expanded I/O
83C453/87C453
LOGIC SYMBOL
VCC XTAL1 VSS
LCC PIN FUNCTIONS
9 1 61
10 PORT 0 ADDRESS AND DATA BUS
60
LCC
XTAL2 26 RST EA/VPP PSEN ALE/PROG RxD TxD INT0 INT1 T0 T1 WR RD PORT 1 44
27 Pin 1 2 3 Function EA/VPP P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 VCC P4.7 P4.6 P4.5 P4.4 P4.3 Pin 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 Function P4.2 P4.1 P4.0 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST P3.0/RxD P3.1/TxD P3.2/INTO P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD P5.0 P5.1 P5.2
43 Pin 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 Function P5.3 P5.4 P5.5 P5.6 P5.7 XTAL2 XTAL1 VSS ODS IDS BFLAG AFLAG P6.0 P6.1 P6.2 P6.3 P6.4 P6.5 P6.6 P6.7 PSEN ALE/PROG
SECONDARY FUNCTIONS
PORT 3
PORT 2
ADDRESS BUS
4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
PORT 6 CONTROL
ODS IDS BFLAG AFLAG
PORT 6
PORT 5
PORT 4
SU00085
SU00157
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Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family 8K/256 OTP/ROM, expanded I/O
83C453/87C453
PIN DESCRIPTION
MNEMONIC VSS VCC P0.0-0.7
PIN NO.
TYPE I I I/O
NAME AND FUNCTION Ground: 0V reference. Power Supply: This is the power supply voltage for normal, idle, and power-down operation. Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 is also the multiplexed data and low-order address bus during accesses to external memory. External pull-ups are required during program verification. Port 0 can sink/source eight LS TTL inputs. Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 receives the low-order address bytes during program memory verification. Port 1 can sink/source three LS TTL inputs, and drive CMOS inputs without external pull-ups. Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 emits the high-order address bytes during access to external memory and receives the high-order address bits and control signals during program verification. Port 2 can sink/source three LS TTL inputs, and drive CMOS inputs without external pull-ups. Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 can sink/source three LS TTL inputs, and drive CMOS inputs without external pull-ups. Port 3 also serves the special functions listed below: RxD (P3.0): Serial input port TxD (P3.1): Serial output port INT0 (P3.2): External interrupt INT1 (P3.3): External interrupt T0 (P3.4): Timer 0 external input T1 (P3.5): Timer 1 external input WR (P3.6): External data memory write strobe RD (P3.7): External data memory read strobe Port 4: Port 4 is an 8-bit bidirectional I/O port with internal pull-ups. Port 4 can sink/source three LS TTL inputs and drive CMOS inputs without external pull-ups. Port 5: Port 5 is an 8-bit bidirectional I/O port with internal pull-ups. Port 5 can sink/source three LS TTL inputs and drive CMOS inputs without external pull-ups. Port 6: Port 6 is a specialized 8-bit bidirectional I/O port with internal pull-ups. This special port can sink/source three LS TTL inputs and drive CMOS inputs without external pull-ups. Port 6 can be used in a strobed or non-strobed mode of operation. Port 6 works in conjunction with four control pins that serve the functions listed below: ODS: Output data strobe IDS: Input data strobe BFLAG: Bidirectional I/O pin with internal pull-ups AFLAG: Bidirectional I/O pin with internal pull-ups Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. An internal pull-down resistor permits a power-on reset using only an external capacitor connected to VCC. Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the address during an access to external memory. ALE is activated at a constant rate of 1/6 the oscillator frequency except during an external data memory access, at which time one ALE is skipped. ALE can sink/source three LS TTL inputs and drive CMOS inputs without external pull-ups. This pin is also the program pulse during EPROM programming. Program Store Enable: The read strobe to external program memory. PSEN is activated twice each machine cycle during fetches from external program memory. However, when executing out of external program memory, two activations of PSEN are skipped during each access to external program memory. PSEN is not activated during fetches from internal program memory. PSEN can sink/source eight LS TTL inputs and drive CMOS inputs without an external pull-up. This pin should be tied low during programming. Instruction Execution Control/Programming Supply Voltage: When EA is held high, the CPU executes out of internal program memory, unless the program counter exceeds 1FFFH. When EA is held low, the CPU executes out of external program memory. EA must never be allowed to float. This pin also receives the 12.75V programming supply voltage (VPP) during EPROM programming. Crystal 1: Input to the inverting oscillator amplifier that forms the oscillator. This input receives the external oscillator when an external oscillator is used. Crystal 2: An output of the inverting amplifier that forms the oscillator. This pin should be floated when an external oscillator is used.
54 18 17-10
P1.0-P1.7
27-34
I/O
P2.0-P2.7
2-9
I/O
P3.0-P3.7
36-43
I/O
36 37 38 39 40 41 42 43 P4.0-P4.3 P4.0-P4.7 P5.0-P5.7 P6.0-P6.7 26-19 44-51 59-66
I O I I I I O O I/O I/O I/O I/O
ODS IDS BFLAG AFLAG RST ALE/PROG
55 56 57 58 35 68
I I I/O I/O I I/O
PSEN
67
O
EA/VPP
1
I
XTAL1 XTAL2
53 52
I O
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Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family 8K/256 OTP/ROM, expanded I/O
83C453/87C453
Table 1.
SYMBOL ACC* B*
87C453 Special Function Registers
DESCRIPTION Accumulator B register DIRECT ADDRESS E0H F0H BIT NAMES AND ADDRESSES MSB E7 F7 EF E6 F6 EE MB0 E5 F5 ED MA1 E4 F4 EC MA0 E3 F3 EB OBFC E2 F2 EA IDSM E1 F1 E9 OBF LSB E0 F0 E8 IBF FCH RESET VALUE 00H 00H
CSR*# DPTR DPH DPL
Port 6 command/status Data pointer (2 bytes) Data pointer high Data pointer low
E8H
MB1
83H 82H BF BE POB BD PIB BC PS BB PT1 BA PX1 B9 PT0 B8 PX0
00H 00H
IP*
Interrupt priority
B8H
-
x0000000B
AUXR#
Auxiliary register
8EH
- AF
- AE IOB B6 96 A6 B6 C6 CE DE SMOD0 D6 AC
- AD IIB 85 95 A5 B5 C5 CD DD - D5 F0
- AC ES 84 94 A4 B4 C4 CC DC POF1 D4 RS1
- AB ET1 83 93 A3 B3 C3 CB DB GF1 D3 RS0
- AA EX1 82 92 A2 B2 C2 CA DA GF0 D2 OV
AF A9 ET0 81 91 A1 B1 C1 C9 D9 PD D1 -
AO A8 EX0 80 90 A0 B0 C0 C8 D8 IDL D0 P
x0000000B
IE* P0* P1* P2* P3* P4*# P5*# P6*# PCON
Interrupt enable Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Power control
A8H 80H 90H A0H B0H C0H C8H D8H 87H
EA 87 97 A7 B7 C7 CF DF SMOD1 D7
00000000B FFH FFH FFH FFH FFH FFH FFH 00xx0000B
PSW* SADDR# SADEN# SBUF
Program status word Slave Address Slave Address Mask Serial data buffer
D0H A9H B9H 99H
CY
00H 00H 00H xxxxxxxxB
9F SCON* SP Serial port control Stack pointer 98H 81H 8F TCON* TMOD TH0 TH1 TL0 TL1 Timer/counter control Timer/counter mode Timer 0 high byte Timer 1 high byte Timer 0 low byte Timer 1 low byte 88H 89H 8CH 8DH 8AH 8BH TF1 GATE SM0
9E SM1
9D SM2
9C REN
9B TB8
9A RB8
99 TI
98 RI 00H 07H
8E TR1 C/T
8D TF0 M1
8C TR0 M0
8B IE1 GATE
8A IT1 C/T
89 IE0 M1
88 IT0 M0 00H 00H 00H 00H 00H 00H
NOTES: * SFRs are bit addressable. # SFRs are modified from or added to the 80C51 SFRs. 1. REset value depends on reset source.
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Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family 8K/256 OTP/ROM, expanded I/O
83C453/87C453
IE REGISTER 0 INT0 1 IT0 IE.0
IP REGISTER
HIGH PRIORITY INTERRUPT
TF0
IE.1
INTERRUPT POLLING SEQUENCE
0 INT1 1 IT1
IE.2
TF1
IE.3
RI TI
IE.4
IE.5 IBF
IE.6 OBF LOW PRIORITY INTERRUPT
INDIVIDUAL ENABLES
GLOBAL DISABLE
SU00562
Figure 1. 8XC453 Interrupt Control System
MSB EA BIT IE.7 IE.6 SYMBOL EA IOB IOB IIB ES ET1 EX1 ET0
LSB EX0
IE.5
IIB
IE.4 IE.3 IE.2 IE.1 IE.0
ES ET1 EX1 ET0 EX0
FUNCTION Disables all interrupts. If EA=0, no interrupt will be acknowledged. If EA=1, each interrupt source is individually enabled or disabled by setting or clearing its enable bit. Enables or disables the Output Buffer Full (OBF) interrupt. If IOB=0, the interrupt is disabled, If IOB=1, an interrupt will occur if EA is set and data has been read from the output buffer register through Port 6 by the external host pulsing ODS low. Enables or disables the Input Buffer Full (IBF) interrupt. If IIB=0, the interrupt is disabled. If IIB=1, an interrupt will occur if EA is set and data has been written into the Port 6 Input Data Buffer by the host strobing IDS low. Enables or disables the Serial Port Interrupt. If ES=0, the Serial Port Interrupt. If ES=0, the Serial Port interrupt is disabled. Enables or disables the Timer 1 Overflow interrupt. If ET1=0, the Timer 1 interrupt is disabled. Enables or disables External Interrupt 1. If EX1=0, External Interrupt 1 is disabled. Enables or disables the Timer 0 Overflow interrupt. If ET0=0, the Timer 0 interrupt is disabled. Enables or disables External Interrupt 0. If EX0=0, external Interrupt 0 is disabled.
SU00563
Figure 2. 8XC453 Interrupt Enable (IE) Register
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Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family 8K/256 OTP/ROM, expanded I/O
83C453/87C453
MSB -- BIT IP.7 IP.6 IP.5 IP.4 IP.3 IP.2 IP.1 IP.0 SYMBOL -- POB PIB PS PT1 PX1 PT0 PX0 POB PIB PS PT1 PX1 PT0
LSB PX0
FUNCTION Reserved. Defines the Output Buffer Full interrupt (IOB) priority level. POB=1 programs it to the higher priority level. Defines the Input Buffer Full interrupt (IIB) priority level. PIB=1 programs it to the higher priority level. Defines the Serial Port interrupt priority level. PS=1 programs it to the higher priority level. Defines the Timer 1 interrupt priority level. PT1=1 programs it to the higher priority level. Defines the External Interrupt 1 priority level. PX1=1 programs it to the higher priority level. Enables or disables the Timer 0 interrupt priority level. PT0=1 programs it to the higher priority level. Defines the External Interrupt 0 priority level. PX0=1 programs it to the higher priority level.
SU00564
Figure 3. 8XC453 Interrupt Priority (IP) Register
7 PCON (87H) BIT PCON.7 PCON.6 PCON.5 PCON.4 PCON.3 PCON.2 PCON.1 PCON.0 SYMBOL SMOD1 SMOD0 -- POF GF1 GF0 PD IDL
6
5 --
4 POF
3 GF1
2 GF0
1 PD
0 IDL
SMOD1 SMOD2
FUNCTION Double Baud rate bit. When set to a 1 and Timer 1 is used to generate baud rate, and the Serial Port is used in modes 1, 2, or 3. If set to 1, SCON.7 will be the Framing Error bit (FE). If PCON.6 is cleared, SCON.7 will be SM0. Reserved. Power Off Flag is set during power on of VCC. If then cleared by software, it can be used to determine if a warm start has occurred. General-purpose flag bit. General-purpose flag bit. Power-Down bit. Setting this bit activates power-down mode. It can only be set if input EW is high. Idle mode bit. Setting this bit activates the idle mode.
If logic 1s are written to PD and IDL at the same time, PD takes precedence.
SU00565
Figure 4. Power Control Register (PCON)
Table 2. Interrupt Table
POLLING PRIORITY 1 2 3 4 5 6 7 SOURCE INTO Timer0 INT1 Timer1 Port 6 Serial I/O Port 6 REQUEST BITS/FLAG IE0 TF0 IE1 TF1 OBF RI,TI IBF VECTOR ADDRESS 03H highest priority 0BH 13H 1BH 33H 23H 2BH lowest priority
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Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family 8K/256 OTP/ROM, expanded I/O
83C453/87C453
SCON Address = 98H Bit Addressable SM0/FE Bit: SM1 SM2 5 REN 4 TB8 3 RB8 2 Tl 1 Rl 0
Reset Value = 0000 0000B
7 6 (SMOD0 = 0/1)*
Symbol FE SM0 SM1
Function Framing Error bit. This bit is set by the receiver when an invalid stop bit is detected. The FE bit is not cleared by valid frames but should be cleared by software. The SMOD0 bit must be set to enable access to the FE bit. Serial Port Mode Bit 0, (SMOD0 must = 0 to access bit SM0) Serial Port Mode Bit 1 SM0 SM1 Mode 0 0 1 1 0 1 0 1 0 1 2 3 Description shift register 8-bit UART 9-bit UART 9-bit UART Baud Rate** fOSC/12 variable fOSC/64 or fOSC/32 variable
SM2
Enables the Automatic Address Recognition feature in Modes 2 or 3. If SM2 = 1 then Rl will not be set unless the received 9th data bit (RB8) is 1, indicating an address, and the received byte is a Given or Broadcast Address. In Mode 1, if SM2 = 1 then Rl will not be activated unless a valid stop bit was received, and the received byte is a Given or Broadcast Address. In Mode 0, SM2 should be 0. Enables serial reception. Set by software to enable reception. Clear by software to disable reception. The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired. In modes 2 and 3, the 9th data bit that was received. In Mode 1, if SM2 = 0, RB8 is the stop bit that was received. In Mode 0, RB8 is not used. Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit in the other modes, in any serial transmission. Must be cleared by software. Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in the other modes, in any serial reception (except see SM2). Must be cleared by software.
REN TB8 RB8 Tl Rl
NOTE: *SMOD0 is located at PCON6. **fOSC = oscillator frequency
SU00043
Figure 5. Serial Port Control Register (SCON)
D0
D1
D2
D3
D4
D5
D6
D7
D8
START BIT
DATA BYTE
ONLY IN MODE 2, 3
STOP BIT
SET FE BIT IF STOP BIT IS 0 (FRAMING ERROR) SM0 TO UART MODE CONTROL
SM0 / FE
SM1
SM2
REN
TB8
RB8
TI
RI
SCON (98H)
SMOD1
SMOD0
-
POF
LVF
GF0
GF1
IDL
PCON (87H)
0 : SCON.7 = SM0 1 : SCON.7 = FE
SU00044
Figure 6. UART Framing Error Detection
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Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family 8K/256 OTP/ROM, expanded I/O
83C453/87C453
D0
D1
D2
D3
D4
D5
D6
D7
D8
SM0 1 1
SM1 1 0
SM2 1
REN 1
TB8 X
RB8
TI
RI
SCON (98H)
RECEIVED ADDRESS D0 TO D7 PROGRAMMED ADDRESS COMPARATOR
IN UART MODE 2 OR MODE 3 AND SM2 = 1: INTERRUPT IF REN=1, RB8=1 AND "RECEIVED ADDRESS" = "PROGRAMMED ADDRESS" - WHEN OWN ADDRESS RECEIVED, CLEAR SM2 TO RECEIVE DATA BYTES - WHEN ALL DATA BYTES HAVE BEEN RECEIVED: SET SM2 TO WAIT FOR NEXT ADDRESS.
SU00045
Figure 7. UART Multiprocessor Communication, Automatic Address Recognition
SPECIAL FUNCTION REGISTER ADDRESSES
Special function register addresses for the device are identical to those of the 80C51, except for the additional registers listed in Table 3.
Enhanced UART
The UART operates in all of the usual modes that are described in the first section of this book for the 80C51. In addition the UART can perform framing error detect by looking for missing stop bits, and automatic address recognition. The 87C453 UART also fully supports multiprocessor communication as does the standard 80C51 UART. When used for framing error detect the UART looks for missing stop bits in the communication. A missing bit will set the FE bit in the SCON register. The FE bit shares the SCON.7 bit with SM0 and the function of SCON.7 is determined by PCON.6 (SMOD0) (see Figure 5). If SMOD0 is set then SCON.7 functions as FE. SCON.7 functions as SM0 when SMOD0 is cleared. When used as FE SCON.7 can only be cleared by software. Refer to Figure 6. Automatic Address Recognition Automatic Address Recognition is a feature which allows the UART to recognize certain addresses in the serial bit stream by using hardware to make the comparisons. This feature saves a great deal of software overhead by eliminating the need for the software to examine every serial address which passes by the serial port. This feature is enabled by setting the SM2 bit in SCON. In the 9 bit UART modes, mode 2 and mode 3, the Receive Interrupt flag (RI) will be automatically set when the received byte contains either the "Given" address or the "Broadcast" address. The 9 bit mode requires that the 9th information bit is a 1 to indicate that the received information is an address and not data. Automatic address recognition is shown in Figure 7. The 8 bit mode is called Mode 1. In this mode the RI flag will be set if SM2 is enabled and the information received has a valid stop bit following the 8 address bits and the information is either a Given or Broadcast address. Mode 0 is the Shift Register mode and SM2 is ignored. Using the Automatic Address Recognition feature allows a master to selectively communicate with one or more slaves by invoking the
Given slave address or addresses. All of the slaves may be contacted by using the Broadcast address. Two special Function Registers are used to define the slave's address, SADDR, and the address mask, SADEN. SADEN is used to define which bits in the SADDR are to b used and which bits are "don't care". The SADEN mask can be logically ANDed with the SADDR to create the "Given" address which the master will use for addressing each of the slaves. Use of the Given address allows multiple slaves to be recognized while excluding others. The following examples will help to show the versatility of this scheme: Slave 0 SADDR = SADEN = Given = SADDR = SADEN = Given = 1100 0000 1111 1101 1100 00X0 1100 0000 1111 1110 1100 000X
Slave 1
In the above example SADDR is the same and the SADEN data is used to differentiate between the two slaves. Slave 0 requires a 0 in bit 0 and it ignores bit 1. Slave 1 requires a 0 in bit 1 and bit 0 is ignored. A unique address for Slave 0 would be 1100 0010 since slave 1 requires a 0 in bit 1. A unique address for slave 1 would be 1100 0001 since a 1 in bit 0 will exclude slave 0. Both slaves can be selected at the same time by an address which has bit 0 = 0 (for slave 0) and bit 1 = 0 (for slave 1). Thus, both could be addressed with 1100 0000. In a more complex system the following could be used to select slaves 1 and 2 while excluding slave 0: Slave 0 SADDR = SADEN = Given = SADDR = SADEN = Given = SADDR = SADEN = Given = 1100 0000 1111 1001 1100 0XX0 1110 0000 1111 1010 1110 0X0X 1110 0000 1111 1100 1110 00XX
Slave 1
Slave 2
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Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family 8K/256 OTP/ROM, expanded I/O
83C453/87C453
In the above example the differentiation among the 3 slaves is in the lower 3 address bits. Slave 0 requires that bit 0 = 0 and it can be uniquely addressed by 1110 0110. Slave 1 requires that bit 1 = 0 and it can be uniquely addressed by 1110 and 0101. Slave 2 requires that bit 2 = 0 and its unique address is 1110 0011. To select Slaves 0 and 1 and exclude Slave 2 use address 1110 0100, since it is necessary t make bit 2 = 1 to exclude slave 2. The Broadcast Address for each slave is created by taking the logical OR of SADDR and SADEN. Zeros in this result are teated as don't-cares. In most cases, interpreting the don't-cares as ones, the broadcast address will be FF hexadecimal. Upon reset SADDR (SFR address 0A9H) and SADEN (SFR address 0B9H) are leaded with 0s. This produces a given address of all "don't cares" as well as a Broadcast address of all "don't cares". this effectively disables the Automatic Addressing mode and allows the microcontroller to use standard 80C51 type UART drivers which do not make use of this feature. The 87C453 UART has all of the capabilities of the standard 80C51 UART plus Framing Error Detection and Automatic Address Recognition. As in the 80C51, all four modes of operation are supported as well as the 9th bit in modes 2 and 3 that can be used to facilitate multiprocessor communication.
does not change the on-chip RAM. An external interrupt allows both the SFRs and the on-chip RAM to retain their values. To properly terminate Power Down the reset or external interrupt should not be executed before VCC is restored to its normal operating level and must be held active long enough for the oscillator to restart and stabilize (normally less than 10ms). With an external interrupt, INT0 and INT1 must be enabled and configured as level-sensitive. Holding the pin low restarts the oscillator but bringing the pin back high completes the exit. Once the interrupt is serviced, the next instruction to be executed after RETI will be the one following the instruction that put the device into Power Down.
Power Off Flag
The Power Off Flag (POF) in PCON is set by on-chip circuitry when the VCC level on the 87C453 rises from 0 to 5V. The POF bit can be set or cleared by software allowing a user to determine if the reset is the result of a power-on or a warm start after powerdown. The VCC level must remain above 3V for the POF to remain unaffected by the VCC level.
Design Consideration
* When the idle mode is terminated by a hardware reset, the device
normally resumes program execution, from where it left off, up to two machine cycles before the internal rest algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory.
OSCILLATOR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier. The pins can be configured for use as an on-chip oscillator. To drive the device from an external clock source, XTAL1 should be driven while XTAL2 is left unconnected. There are no requirements on the duty cycle of the external clock signal, because the input to the internal clock circuitry is through a divide-by-two flip-flop. However, minimum and maximum high and low times specified in the data sheet must be observed.
ONCETM Mode
The ONCE ("On-Circuit Emulation") Mode facilitates testing and debugging of systems using the 87C453 without having to remove the IC from the circuit. The ONCE Mode is invoked by: 1. Pull ALE low while the device is in reset and PSEN is high; 2. Hold ALE low as RST is deactivated. While the device is in ONCE Mode, the Port 0 pins go into a float state, and the other port pins and ALE and PSEN are weakly pulled high. The oscillator circuit remains active. While the 87C453 is in this mode, an emulator or test CPU can be used to drive the circuit. Normal operation is restored when a normal reset is applied.
Reset
A reset is accomplished by holding the RST pin high for at least two machine cycles (24 oscillator periods), while the oscillator is running. To insure a good power-on reset, the RST pin must be high long enough to allow the oscillator time to start up (normally a few milliseconds) plus two machine cycles. At power-on, the voltage on VCC and RST must come up at the same time for a proper start-up.
Idle Mode
In the idle mode, the CPU puts itself to sleep while all of the on-chip peripherals stay active. The instruction to invoke the idle mode is the last instruction executed in the normal operating mode before the idle mode is activated. The CPU contents, the on-chip RAM, and all of the special function registers remain intact during this mode. The idle mode can be terminated either by any enabled interrupt (at which time the process is picked up at the interrupt service routine and continued), or by a hardware reset which starts the processor in the same manner as a power-on reset.
PORTS 4 AND 5
Ports 4 and 5 are bidirectional I/O ports with internal pull-ups. Port 4 is an 8-bit port. Port 4 and port 5 pins with ones written to them, are pulled high by the internal pull-ups, and in that state can be used as inputs. Ports 4 and 5 are addressed at the special function register addresses shown in Table 3.
PORT 6
Port 6 is a special 8-bit bidirectional I/O port with internal pull-ups (see Figure 8). This port can be used as a standard I/O port, or in strobed modes of operation in conjunction with four special control lines: ODS, IDS, AFLAG, and BFLAG. Port 6 operating modes are controlled by the port 6 control status register (CSR). Port 6 and the CSR are addressed at the special function register addresses shown in Table 3. The following four control pins are used in conjunction with port 6: ODS - Output data strobe for port 6. ODS can be programmed to control the port 6 output drivers and the output buffer full flag (OBF), or to clear only the OBF flag bit in the CSR (output-always mode).
Power-Down Mode
To save even more power, a Power Down mode can be invoked by software. In this mode, the oscillator is stopped and the instruction that invoked Power Down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the Power Down mode is terminated. On the 87C453 either a hardware reset or external interrupt can cause an exit from Power Down. Reset redefines all the SFRs but
1998 Apr 23
11
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family 8K/256 OTP/ROM, expanded I/O
83C453/87C453
ODS is active low for output driver control. The OBF flag can be programmed to be cleared on the negative or positive edge of ODS. Can produce an IOB interrupt (see Figure 2). IDS - Input data strobe for port 6. IDS is used to control the port 6 input latch and input buffer full flag (IBF) bit in the CSR. The input data latch can be programmed to be transparent when IDS is low and latched on the positive transition of IDS, or to latch only on the positive transition of IDS. Correspondingly, the IBF flag is set on the negative or positive transition of IDS. Can produce an IIB interrupt (see Figure 2). AFLAG - AFLAG is a bidirectional I/O pin which can be programmed to be an output set high or low under program control, or to output the state of the output buffer full flag. AFLAG can also be programmed to be an input which selects whether the contents of the output buffer, or the contents of the port 6 control status register will output on port 6. This feature grants complete port 6 status to external devices. BFLAG - BFLAG is a bidirectional I/O pin which can be programmed to be an output, set high or low under program control, or to output the state of the input buffer full flag. BFLAG can also be programmed to input an enable signal for port 6. When BFLAG is used as an enable input, port 6 output drivers are in the high-impedance state, and the input latch does not respond to the IDS strobe when BFLAG is high. Both features are enabled when BFLAG is low. This feature facilitates the use of the 87C453 in bused multiprocessor systems.
CSR.3 Output Buffer Full Flag Clear Mode (OBFC) - When CSR.3 = 1, the positive edge of the ODS input clears the OBF flag. When CSR.3 = 0, the negative edge of the ODS input clears the OBF flag. CSR.4, CSR.5 AFLAG Mode Select (MA0, MA1) - Bits 4 and 5 select the mode of operation for the AFLAG pin as follows: MA1 0 0 1 1 MA0 0 1 0 1 AFLAG Function Logic 0 output Logic 1 output OBF flag output (CSR.1) Select (SEL) input mode
The select (SEL) input mode is used to determine whether the port 6 data register or the control status register is output on port 6. When the select feature is enabled, the AFLAG input controls the source of port 6 output data. A logic 0 on AFLAG input selects the port 6 data register, and a logic 1 on AFLAG input selects the control status register. The value of the AFLAG input is latched into the Auxiliary Register (AUXR) bit 1 (AUXR.1). Checking this bit (AF) will allow the 87C453's program to determine if Port 6 was loaded with data or a UPI command. CSR.6, CSR.7 BFLAG Mode Select (MB0, MB1) - Bits 6 and 7 select the mode operation as follows: MB1 MB0 0 0 0 1 1 0 1 1 BFLAG Function Logic 0 output Logic 1 output IBF flag output (CSR.0) Port enable (PE)
CONTROL STATUS REGISTER
The control status register (CSR) establishes the mode of operation for port 6 and indicates the current status of port 6 I/O registers. All control status register bits can be read and written by the CPU, except bits 0 and 1, which are read only. Reset writes ones to bits 2 through 7, and writes zeros to bits 0 and 1 (see Table 4). CSR.0 Input Buffer Full Flag (IBF) (Read Only) - The IBF bit is set to a logic 1 when port 6 data is loaded into the input buffer under control of IDS. This can occur on the negative or positive edge of IDS, as determined by CSR.2. When IBF is set, the Interrupt Enable Register bit IIB (IE.5) is set. The Interrupt Service Routine vector address for this interrupt is 002BH. IBF is cleared when the CPU reads the input buffer register. CSR.1 Output Buffer Full Flag (OBF) (Read Only) - The OBF flag is set to a logic 1 when the CPU writes to the port 6 output data buffer. OBF is cleared by the positive or negative edge of ODS, as determined by CSR.3. When OBF is cleared, the Interrupt Enable Register bit IOB (IE.6) is set. The Interrupt Service Routine vector address for this interrupt is 0033H. CSR.2 IDS Mode Select (IDSM) - When CSR.2 = 0, a low-to-high transition on the IDS pin sets the IBF flag. The Port 6 input buffer is loaded on the IDS positive edge. When CSR.2 = 1, a high-to-low transition on the IDS pin sets the IBF flag. Port 6 input buffer is transparent when IDS is low, and latched when IDS is high.
In the port enable mode, IDS and ODS inputs are disabled when BFLAG input is high. When the BFLAG input is low, the port is enabled for I/O. Reduced EMI Mode - The on-chip clock distribution drivers have been identified as the cause of most of the EMI emissions from the 80C51 family. By tailoring the clock drivers properly, a compromise between maximum operating speed and minimal EMI emissions can be achieved. Typically, an order in magnitude of reduction is possible over previous designs. This feature has been implemented on this chip along with the additional capability of turning off the ALE output. Setting the AO bit (AUXR.0) in the AUXR special function register will disable the ALE output. Reset forces a 0 into AUXR.0 to enable normal 80C51 type operation. Auxiliary Register (AUXR) 7 6 5 4 - - - -
3 -
2 -
1 AF
0 AO
Latched value of AFLAG when Port 6 inputs data from IDS strobe 0 = ALE enabled 1 = ALE disabled
1998 Apr 23
12
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family 8K/256 OTP/ROM, expanded I/O
83C453/87C453
AFLAG
BFLAG ODS
PORT 6
IDS
BFLAG/ODS MODE (CSR.6/.7)
OUTPUT DRIVERS
INPUT BUFFER (P6 READ)
IDS MODE
AFLAG MODE (CSR.4/.5)
INPUT BUFFER FULL (CSR.0) MUX EDGE/LEVEL SELECT (CSR.2)
OUTPUT BUFFER FULL (CSR.1) CONTROL/STATUS REGISTER (CSR) OUTPUT BUFFER (P6 WRITE)
INTERNAL BUS
SU00087
Figure 8. Port 6 Block Diagram
Table 3. Special Function Register Addresses
REGISTER ADDRESS Name Port 4 Port 5 Port 6 data Port 6 control status Slave address Slave address mask Auxiliary Register Symbol P4 P5 P6 CSR SADDR SADEN AUXR Address C0 C8 D8 E8 A9 B9 8E MSB C7 CF DF EF C6 CE DE EE C5 CD DD ED C4 CC DC EC C3 CB DB EB C2 CA DA EA C1 C9 D9 E9 BIT ADDRESS LSB C0 C8 D8 E8
Table 4. Control Status Register (CSR)
Bit 7 MB1 Bit 6 MB0 Bit 5 MA1 Bit 4 MA0 Bit 3 OBFC Output Buffer Flag Clear Mode 0 = Negative edge of ODS 1 = Positive edge o ODS Bit 2 IDSM Input Data Strobe Mode 0 = Positive edge of IDS 1 = Low level of IDS Bit 1 OBF Output Buffer Flag Full 0 = Output data buffer empty 1 = Output data buffer full Bit 0 IBF Input Buffer Flag Full 0 = Input data buffer empty 1 = Input data buffer full
BFLAG Mode Select
AFLAG Mode Select
0/0 = Logic 0 output* 0/1 = Logic 1 output* 1/0 = IBF output 1/1 = PE input (0 = Select) (1 = Disable I/O)
0/0 = Logic 0 output* 0/1 = Logic 1 output* 1/0 = OBF output 1/1 = SEL input (0 = Select) (1 = Control/status)
NOTE: * Output-always mode: MB1 = 0, MA1 = 1, and MA0 = 0. In this mode, port 6 is always enabled for output. ODS only clears the OBF flag.
1998 Apr 23
13
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family 8K/256 OTP/ROM, expanded I/O
83C453/87C453
ABSOLUTE MAXIMUM RATINGS1, 2, 3
PARAMETER Operating temperature under bias Storage temperature range Voltage on any other pin to VSS Power dissipation (based on package heat transfer limitations, not device power consumption) RATING 0 to +70 -65 to +150 -0.5 to +6.5 1.5 UNIT C C V W
NOTES: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section of this specification is not implied. 2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima. 3. Parameters are valid over operating temperature range unless otherwise specified. Voltages are with respect to VSS unless otherwise noted.
DC ELECTRICAL CHARACTERISTICS
Tamb = 0C to +70C, VCC = 5V 10%, VSS = 0V SYMBOL VIL VIL1 VIH VIH1 VOL VOL1 VOH PARAMETER Input low voltage; ports 0, 1, 2, 3, 4, 5, 6, IDS, ODS, AFLAG, BFLAG; except EA Input low voltage to EA Input high voltage; except XTAL1, RST Input high voltage; XTAL1, RST Output low voltage; ports 1, 2, 3, 4, 5, 6, AFLAG, BFLAG Output low voltage; port 0, ALE, PSEN Output high voltage; ports 1, 2, 3, 4, 5, 6, AFLAG, BFLAG Output high voltage (port 0 in external bus mode, ALE, PSEN)3 Logical 0 input current,; ports 1, 2, 3, 4, 5, 6 Logical 1-to-0 transition current; ports 1, 2, 3, 4, 5, 6 Input leakage current; port 0 Power supply current: Active mode @ 16MHz5 Idle mode @ 16MHz5 Power down mode Internal reset pull-down resistor IOL = 1.6mA2 IOL = 3.2mA2 IOH = -60A, IOH = -25A IOH = -10A IOH = -800A, IOH = -300A IOH = -80A VIN = 0.45V See note 4 VIN = VIL or VIH See note 6 11.5 1.3 3 50 25 4 50 300 mA mA A k 2.4 0.75VCC 0.9VCC 2.4 0.75VCC 0.9VCC -50 -650 10 TEST CONDITIONS MIN -0.5 0 0.2VCC+0.9 0.7VCC LIMITS TYP1 MAX 0.2VCC-0.1 0.2VCC-0.3 VCC+0.5 VCC+0.5 0.45 0.45 UNIT V V V V V V V V V V V V A A A
VOH1
IIL ITL ILI ICC
RRST
CIO Pin capacitance7 - PLCC package 10 pF NOTES: 1. Typical ratings are based on a limited number of samples from early manufacturing lots, and not guaranteed. Values are room temp., 5V. 2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the VOLs of ALE and the other ports. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input.. 3. Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9VCC specification when the address bits are stabilizing. 4. Pins of ports 1, 2, 3, 4, 5 and 6 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value when VIN is approximately 2V. 5. ICCMAX at other frequencies is given by: Active mode: ICCMAX = 0.94 X FREQ + 13.71 Idle mode: ICCMAX = 0.14 X FREQ +2.31 where FREQ is the external oscillator frequency in MHz. ICCMAX is given in mA. See Figure 20. 6. See Figures 21 through 24 for ICC test conditions. 7. CIO applies to ports 1 through 6, IDS, ODS, AFLAG, BFLAG, XTAL1, XTAL2.
1998 Apr 23
14
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family 8K/256 OTP/ROM, expanded I/O
83C453/87C453
AC ELECTRICAL CHARACTERISTICS
Tamb = 0C to +70C, VCC = 5V 10%, VSS = 0V 16MHz CLOCK SYMBOL 1/tCLCL tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ tAVIV tPLAZ Data Memory tRLRH tWLWH tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tQVWX tWHQX tRLAZ tWHLH Shift Register tXLXL tQVXH tXHQX tXHDX tXHDV 12 12 12 12 12 Serial port clock cycle time Output data setup to clock rising edge Output data hold after clock rising edge Input data hold after clock rising edge Clock rising edge to input data valid 750 492 8 0 492 12tCLCL 10tCLCL-133 2tCLCL-117 0 10tCLCL-133 ns ns ns ns ns 10, 11 10, 11 10, 11 10, 11 10, 11 10, 11 10, 11 10, 11 10, 11 10, 11 10, 11 10, 11 10, 11 RD pulse width WR pulse width RD low to valid data in Data hold after RD Data float after RD ALE low to valid data in Address to valid data in ALE low to RD or WR low Address valid to WR low or RD low Data valid to WR transition Data hold after WR RD low to address float RD or WR high to ALE high 23 137 122 13 13 0 103 tCLCL-40 0 65 350 397 239 3tCLCL-50 4tCLCL-130 tCLCL-50 tCLCL-50 0 tCLCL+40 275 275 147 0 2tCLCL-60 8tCLCL-150 9tCLCL-165 3tCLCL+50 6tCLCL-100 6tCLCL-100 5tCLCL-165 ns ns ns ns ns ns ns ns ns ns ns ns ns 9 9 9 9 9 9 9 9 9 9 9 FIGURE PARAMETER Oscillator frequency ALE pulse width Address valid to ALE low Address hold after ALE low ALE low to valid instruction in ALE low to PSEN low PSEN pulse width PSEN low to valid instruction in Input instruction hold after PSEN Input instruction float after PSEN Address to valid instruction in PSEN low to address float 0 37 207 10 32 142 82 0 tCLCL-25 5tCLCL-105 10 85 22 32 150 tCLCL-30 3tCLCL-45 3tCLCL-105 MIN MAX VARIABLE CLOCK MIN 3.5 2tCLCL-40 tCLCL-40 tCLCL-30 4tCLCL-100 MAX 16 UNIT MHz ns ns ns ns ns ns ns ns ns ns ns
Port 6 input (input rise and fall times = 5ns) tFLFH tILIH tDVIH tIHDZ tIVFV 15 15 15 15 16 PE width IDS width Data setup to IDS high or PE high Data hold after IDS high or PE high IDS to BFLAG (IBF) delay 209 209 0 30 130 3tCLCL+20 3tCLCL+20 0 30 130 ns ns ns ns ns
1998 Apr 23
15
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family 8K/256 OTP/ROM, expanded I/O
83C453/87C453
AC ELECTRICAL CHARACTERISTICS (Continued)
16MHz CLOCK SYMBOL FIGURE PARAMETER MIN MAX VARIABLE CLOCK MIN MAX UNIT
Port 6 output tOLOH tFVDV tOLDV tOHDZ tOVFV tFLDV tOHFH External Clock tCHCX tCLCX tCLCH tCHCL 17 17 17 17 High time Low time Rise time Fall time 20 20 20 20 20 20 20 20 ns ns ns ns 13 14 13 13 13 13 14 ODS width SEL to data out delay ODS to data out delay ODS to data float delay ODS to AFLAG (OBF) delay PE to data out delay ODS to AFLAG (SEL) delay 100 209 85 80 35 100 120 100 3tCLCL+20 85 80 35 100 120 ns ns ns ns ns ns ns
NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
1998 Apr 23
16
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family 8K/256 OTP/ROM, expanded I/O
83C453/87C453
EXPLANATION OF THE AC SYMBOLS
Each timing symbol has five characters. The first character is always `t' (= time). The other characters, depending on their positions, indicate the name of a signal or the logical status of that signal. The designations are: A - Address C - Clock D - Input data H - Logic level high I - Instruction (program memory contents) L - Logic level low, or ALE P - PSEN Q - Output data R - RD signal t - Time V - Valid W - WR signal X - No longer a valid logic level Z - Float Examples: tAVLL = Time for address valid to ALE low. tLLPL = Time for ALE low to PSEN low.
tLHLL
ALE
tAVLL
tLLPL tLLIV
tPLPH tPLIV tPLAZ tPXIX
INSTR IN
PSEN
tPXIZ
tLLAX
PORT 0 A0-A7
A0-A7
tAVIV
PORT 2 A0-A15 A8-A15
SU00056
Figure 9. External Program Memory Read Cycle
ALE
tWHLH
PSEN
tLLDV tLLWL
RD
tRLRH
tAVLL
PORT 0
tLLAX tRLAZ
A0-A7 FROM RI OR DPL
tRLDV tRHDX
DATA IN
tRHDZ
A0-A7 FROM PCL
INSTR IN
tAVWL tAVDV
PORT 2 P2.0-P2.7 OR A8-A15 FROM DPH A0-A15 FROM PCH
SU00007
Figure 10. External Data Memory Read Cycle
1998 Apr 23
17
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family 8K/256 OTP/ROM, expanded I/O
83C453/87C453
ALE
tWHLH
PSEN
tLLWL
WR
tWLWH
tAVLL
PORT 0
tLLAX
tQVWX
tWHQX
A0-A7 FROM RI OR DPL
DATA OUT
A0-A7 FROM PCL
INSTR IN
tAVWL
PORT 2 P2.0-P2.7 OR A8-A15 FROM DPH A0-A15 FROM PCH
SU00008
Figure 11. External Data Memory Write Cycle
INSTRUCTION ALE
0
1
2
3
4
5
6
7
8
tXLXL
CLOCK
tQVXH
OUTPUT DATA 0 WRITE TO SBUF
tXHQX
1 2 3 4 5 6 7
tXHDV
INPUT DATA VALID CLEAR RI VALID
tXHDX
SET TI VALID VALID VALID VALID VALID VALID
SET RI
SU00027
Figure 12. Shift Register Mode Timing
1998 Apr 23
18
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family 8K/256 OTP/ROM, expanded I/O
83C453/87C453
OBF (AFLAG)
tOVFV
PE (BFLAG)
tOVFV
tOLOH
ODS
tOLDV
PORT 6
tOHDZ
tFLDV
SU00088
Figure 13. Port 6 Output
ODS
tOHFH
SEL (AFLAG)
tFVDV
tFVDV
PORT 6
DATA
CSR
DATA
SU00089
Figure 14. Port 6 Select Mode
tFLFH
PE (BFLAG)
tILIH
IDS
tDVIH
PORT 6
tIHDZ
SU00090
Figure 15. Port 6 Input
IBF (BFLAG)
tIVFV
IDS
tIVFV
SU00091A
Figure 16. IBF Flag Output
1998 Apr 23
19
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family 8K/256 OTP/ROM, expanded I/O
83C453/87C453
VCC-0.5 0.45V
0.7VCC 0.2VCC-0.1
tCHCL
tCLCX tCLCL
tCHCX tCLCH
SU00009
Figure 17. External Clock Drive
VCC-0.5
0.2VCC+0.9 VLOAD 0.2VCC-0.1
VLOAD+0.1V VLOAD-0.1V
TIMING REFERENCE POINTS
VOH-0.1V VOL+0.1V
0.45V
NOTE: AC inputs during testing are driven at VCC -0.5 for a logic `1' and 0.45V for a logic `0'. Timing measurements are made at VIH min for a logic `1' and VIL max for a logic `0'.
NOTE: For timing purposes, a port is no longer floating when a 100mV change from load voltage occurs, and begins to float when a 100mV change from the loaded VOH/VOL level occurs. IOH/IOL 20mA.
SU00717
SU00718
Figure 18. AC Testing Input/Output
Figure 19. Float Waveform
30
MAX ACTIVE MODE
25
20
ICC mA
15
TYP ACTIVE MODE
10
5
MAX IDLE MODE TYP IDLE MODE 4MHz 8MHz 12MHz 16MHz
FREQ AT XTAL1 VALID ONLY WITHIN FREQUENCY SPECIFICATIONS OF THE DEVICE UNDER TEST.
SU00092
Figure 20. ICC vs. FREQ
1998 Apr 23
20
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family 8K/256 OTP/ROM, expanded I/O
83C453/87C453
VCC ICC VCC VCC P0 EA (NC) CLOCK SIGNAL XTAL2 XTAL1 IDS VSS ODS VSS IDS ODS VCC (NC) CLOCK SIGNAL XTAL2 XTAL1 VCC RST P0 EA VCC
VCC ICC
VCC
RST
VCC
SU00093
SU00094
Figure 21. ICC Test Condition, Active Mode All other pins are disconnected
Figure 22. ICC Test Condition, Idle Mode All other pins are disconnected
VCC-0.5 0.45V
0.7VCC 0.2VCC-0.1
tCHCL
tCLCX tCLCL
tCHCX tCLCH
SU00009
Figure 23. Clock Signal Waveform for ICC Tests in Active and Idle Modes tCLCH = tCHCL = 5ns
VCC ICC VCC RST P0 EA (NC) XTAL2 XTAL1 VSS IDS ODS VCC VCC
SU00095
Figure 24. ICC Test Condition, Power Down Mode All other pins are disconnected. VCC = 2V to 5.5V
1998 Apr 23
21
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family 8K/256 OTP/ROM, expanded I/O
83C453/87C453
EPROM CHARACTERISTICS
The 87C453 is programmed by using a modified Quick-Pulse ProgrammingTM algorithm. It differs from older methods in the value used for VPP (programming supply voltage) and in the width and number of the ALE/PROG pulses. The 87C453 contains two signature bytes that can be read and used by an EPROM programming system to identify the device. The signature bytes identify the device as an 87C453 manufactured by Philips Semiconductors. Table 5 shows the logic levels for reading the signature byte, and for programming the program memory, the encryption table, and the lock bits. The circuit configuration and waveforms for quick-pulse programming are shown in Figures 25 and 26. Figure 27 shows the circuit configuration for normal program memory verification.
Program Verification If lock bit 2 has not been programmed, the on-chip program memory can be read out for program verification. The address of the program memory locations to be read is applied to ports 1 and 2 as shown in Figure 27. The other pins are held at the `Verify Code Data' levels indicated in Table 5. The contents of the address location will be emitted on port 0. External pull-ups are required on port 0 for this operation. If the encryption table has been programmed, the data presented at port 0 will be the exclusive NOR of the program byte with one of the encryption bytes. The user will have to know the encryption table contents in order to correctly decode the verification data. The encryption table itself cannot be read out. Reading the Signature Bytes The signature bytes are read by the same procedure as a normal verification of locations 030H and 031H, except that P3.6 and P3.7 need to be pulled to a logic low. The values are: (030H) = 15H indicates manufactured by Philips (031H) = B9H indicates 87C453
Quick-Pulse Programming
The setup for microcontroller quick-pulse programming is shown in Figure 26. Note that the 87C453 is running with a 4 to 6MHz oscillator. The reason the oscillator needs to be running is that the device is executing internal address and program data transfers. The address of the EPROM location to be programmed is applied to ports 1 and 2, as shown in Figure 25. The code byte to be programmed into that location is applied to port 0. RST, PSEN and pins of ports 2 and 3 specified in Table 5 are held at the `Program Code Data' levels indicated in Table 5. The ALE/PROG is pulsed low 15 to 25 times, as shown in Figure 26. To program the encryption table, repeat the 15 to 25 pulse programming sequence for addresses 0 through 1FH, using the `Pgm Encryption Table' levels. Do not forget that after the encryption table is programmed, verification cycles will produce only encrypted data. To program the lock bits, repeat the 15 to 25 pulse programming sequence using the `Pgm Lock Bit' levels. After one lock bit is programmed, further programming of the code memory and encryption table is disabled. However, the other lock bit can still be programmed. Note that the EA/VPP pin must not be allowed to go above the maximum specified VPP level for any amount of time. Even a narrow glitch above that voltage can cause permanent damage to the device. The VPP source should be well regulated and free of glitches and overshoot.
Program/Verify Algorithms
Any algorithm in agreement with the conditions listed in Table 5, and which satisfies the timing specifications, is suitable.
Erasure Characteristics
Erasure of the EPROM begins to occur when the chip is exposed to light with wavelengths shorter than approximately 4,000 angstroms. Since sunlight and fluorescent lighting have wavelengths in this range, exposure to these light sources over an extended time (about 1 week in sunlight, or 3 years in room level fluorescent lighting) could cause inadvertent erasure. For this and secondary effects, it is recommended that an opaque label be placed over the window. For elevated temperature or environments where solvents are being used, apply Kapton tape Fluorglas part number 2345-5, or equivalent. The recommended erasure procedure is exposure to ultraviolet light (at 2537 angstroms) to an integrated dose of at least 15W-sec/cm2. Exposing the EPROM to an ultraviolet lamp of 12,000W/cm2 rating for 20 to 39 minutes, at a distance of about 1 inch, should be sufficient. Erasure leaves the array in an all 1s state.
Table 5. EPROM Programming Modes
MODE Read signature Program code data Verify code data Pgm encryption table Pgm lock bit 1 RST 1 1 1 1 1 PSEN 0 0 0 0 0 ALE/PROG 1 0* 1 0* 0* EA/VPP 1 VPP 1 VPP VPP P2.7 0 1 0 1 1 P2.6 0 0 0 0 1 P3.7 0 1 1 1 1 P3.6 0 1 1 0 1
Pgm lock bit 2 1 0 0* VPP 1 1 0 0 NOTES: 1. `0' = Valid low for that pin, `1' = valid high for that pin. 2. VPP = 12.75V 0.25V. 3. VCC = 5V 10% during programming and verification. * ALE/PROG receives 15 to 25 programming pulses while VPP is held at 12.75V. Each programming pulse is low for 100s (10s) and high for a minimum of 10s. TMTrademark phrase of Intel Corporation. 1998 Apr 23 22
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family 8K/256 OTP/ROM, expanded I/O
83C453/87C453
+5V VCC A0-A7 1 1 1 P1 RST P3.6 P3.7 XTAL2 4-6MHz XTAL1 VSS 87C453 P0 PGM DATA +12.75V 15 TO 25 100s PULSES TO GROUND 0 1 0 A8-A12
EA/VPP ALE/PROG PSEN P2.7 P2.6 P2.0-P2.4
SU00159
Figure 25. Programming Configuration
15 TO 25 PULSES 1 ALE/PROG: 0
10s MIN 1 ALE/PROG: 0
100s+10
SU00160
Figure 26. PROG Waveform
+5V
VCC A0-A7 1 1 1 P1 RST P3.6 P3.7 XTAL2 4-6MHz XTAL1 VSS 87C453 P0 PGM DATA 1 1 0 0 ENABLE 0 A8-A12
EA/VPP ALE/PROG PSEN P2.7 P2.6 P2.0-P2.4
SU00161
Figure 27. Program Verification
1998 Apr 23
23
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family 8K/256 OTP/ROM, expanded I/O
83C453/87C453
EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS
Tamb = 21C to +27C, VCC = 5V10%, VSS = 0V (See Figure 28) SYMBOL VPP IPP 1/tCLCL tAVGL tGHAX tDVGL tGHDX tEHSH tSHGL tGHSL tGLGH tAVQV tELQZ tEHQZ tGHGL PARAMETER Programming supply voltage Programming supply current Oscillator frequency Address setup to PROG low Address hold after PROG Data setup to PROG low Data hold after PROG P2.7 (ENABLE) high to VPP VPP setup to PROG low VPP hold after PROG PROG width Address to data valid ENABLE low to data valid Data float after ENABLE PROG high to PROG low 0 10 4 48tCLCL 48tCLCL 48tCLCL 48tCLCL 48tCLCL 10 10 90 110 48tCLCL 48tCLCL 48tCLCL s s s s MIN 12.5 MAX 13.0 50 6 UNIT V mA MHz
PROGRAMMING* P1.0-P1.7 P2.0-P2.4 ADDRESS
VERIFICATION* ADDRESS
tAVQV
PORT 0 DATA IN DATA OUT
tDVGL tAVGL
ALE/PROG
tGHDX tGHAX
tGLGH tSHGL
tGHGL tGHSL
LOGIC 1 EA/VPP LOGIC 0
LOGIC 1
tEHSH
P2.7 ENABLE
tELQV
tEHQZ
SU00020
NOTE: * FOR PROGRAMMING VERIFICATION SEE FIGURE 25.
FOR VERIFICATION CONDITIONS SEE FIGURE 27.
Figure 28. EPROM Programming and Verification
1998 Apr 23
24
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family 8K/256 OTP/ROM, expanded I/O
83C453/87C453
PLCC68: plastic leaded chip carrier; 68 leads; pedestal
SOT188-3
1998 Apr 23
25
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family 8K/256 OTP/ROM, expanded I/O
83C453/87C453
Data sheet status
Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Production
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Date of release: 05-98 Document order number: 9397 750 03886
Philips Semiconductors
1998 Apr 23 26

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